External Trigger Pulse Mode (Tpnmd2 To Tpnmd0 = 010) - NEC V850E/RS1 User Manual

7.5.4 External trigger pulse mode (TPnMD2 to TPnMD0 = 010)

When TPnCE = 1 in the external trigger pulse mode, the 16-bit counter stops at FFFFH and waits for
input of an external trigger (TIPn0 pin input). When the counter detects the edge of the external trigger
(TIPn0 pin input), it starts counting up.
The duty factor of the signal output from the TOPn1 pin is set by a reload register (TPnCCR1) and the
period is set by a compare register (TPnCCR0).
Rewriting the TPnCCR0 and TPnCCR1 registers is enabled when TPnCE = 1.
So that the set values of the TPnCCR0 and TPnCCR1 registers after rewriting are compared with the
value of the 16-bit counter (reloaded to the CCRm buffer register), the TPnCCR0 register must be
rewritten and then a value is written to the TPnCCR1 register before the value of the 16-bit counter
matches the value of the TPnCCR0 register.
When the value of the TPnCCR0 register later matches the value of the 16-bit counter, the values of the
TPnCCR0 and TPnCCR1 registers are reloaded to the CCRm buffer register.
Whether the next reload timing is made valid or not is controlled by writing to the TPnCCR1 register.
Therefore, write the same value to the TPnCCR1 register when it is necessary to rewrite the value of
only the TPnCCR0 register.
Reload is invalid when only the TPnCCR0 register is rewritten. To stop timer P, clear TPnCE to 0. If the
edge of the external trigger (TIPn0 pin input) is detected more than once in the external trigger pulse
mode, the 16-bit counter is cleared at the point of edge detection, and resumes counting up. To realize
the same function as the external trigger pulse mode by using a software trigger instead of the external
trigger input (TIPn0 pin input) (software trigger pulse mode), a software trigger is generated by setting
the TPnEST bit of the TPnCTL1 register to 1. The waveform of the external trigger pulse is output from
TOPn1. A toggle output is produced from the TOPn0 pin when the value of the TPnCCR0 register
matches the value of the 16-bit counter.
In the external trigger pulse mode, the capture function of the TPnCCR0 and TPnCCR1 registers
cannot be used because these registers can be used only as compare registers.
Caution:
Remarks: 1. For the reload operation when TPnCCR0 and TPnCCR1 are rewritten during timer
Downloaded from Elcodis.com electronic components distributor
Chapter 7 16-Bit Timer/Event Counter P
In the external trigger pulse mode, select the internal clock (TPnEEE bit of TPnCTL1
register = 0) for the count clock.
operation, refer to section 7.5.6 PWM mode (TPnMD2 to TPnMD0 = 100).
2. n = 0 to 3
m = 0, 1
User's Manual U16702EE3V2UD00 281