NEC V850E/RS1 User Manual page 258

(1) TMP capture/compare register 0 (TPnCCR0)
The TPnCCR0 register is a 16-bit register that operates either as capture register or as a compare
register.
Whether this register is used as a capture register or as a compare register can be specified with
the TPnCCS1 and TPnCCSS0 bits of the TMPn option register 0 (TPnOPT0 register), but only in
the free-running mode.
In the pulse width measurement mode, this register can be used only as a capture register (the
compare function cannot be used.)
In all modes other than free-running mode and pulse width measurement mode, this register is
used as a compare register.
After a RESET, TPnCCR0 register default status is compare register.
RESET input clears this register to 0000H.
Caution:
Address: TP0CCR0: FFFFF596H, TP1CCR0: FFFFF5A6H,
TPnCCR0
Remark:
• When used as a compare register
TPnCCR0 can be rewritten when TPnCE = 1, as below mentioned.
PWM mode, external trigger pulse output mode
Free-running mode, external event count mode,
one-shot pulse mode, interval timer mode
Pulse width measurement mode
• When used as capture register
Count value is stored in TPnCCR0 upon capture trigger (TIPn0) input edge detection.
Note: The value of TPnCCR0 register is read when TPnCE bit of TMPn control register 0 (TPnCTL0)
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Chapter 7 16-Bit Timer/Event Counter P
When external event counter mode is used, do not set TPnCCR0 register to 0000H.
Figure 7-2: Capture/Compare Register 0 (TPnCCR0) Format
TP2CCR0: FFFFF5B6H, TP3CCR0: FFFFF5C6H
15 14 13 12 11 10
n = 0 to 3
TMP operation mode
equals 1.
9 8 7 6 5 4
TPnCCR0 register writing method
Reload
Any time write
Cannot be used because it is only used as capture
register
User's Manual U16702EE3V2UD00
3 2 1 0 Address
FFFF F596H
to
FFFF F5C6H
Initial
R/W
value
R/W 0000H