NEC V850E/RS1 User Manual page 17

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List of Tables
Pin Configuration ......................................................................................................... 33
Internal Block Diagram ................................................................................................ 35
Pin I/O Circuits ............................................................................................................ 60
CPU Register Set ........................................................................................................ 62
Program Counter (PC) Format .................................................................................... 63
Interrupt Status Saving Registers (EIPC and EIPSW) Format .................................... 65
NMI Status Saving Registers (FEPC and FEPSW) Format ........................................ 66
Interrupt Source Register (ECR) Format ..................................................................... 66
Program Status Word (PSW) Format (1/2).................................................................. 67
CALLT Execution Status Saving Registers (CTPC and CTPSW) Format................... 68
Exception/Debug Trap Status Saving Registers (DBPC and DBPSW) Format .......... 69
CALLT Base Pointer (CTBP) Format .......................................................................... 69
Command Register (PRCMD) Format ........................................................................ 72
System Status Register (SYS) Format ....................................................................... 73
CPU Address Space ................................................................................................... 75
Image on Address Space ............................................................................................ 76
Program Space ........................................................................................................... 77
Data Space.................................................................................................................. 77
Data Memory Map (Physical Addresses) .................................................................... 78
Program Memory Map................................................................................................. 79
Memory Map Area for µPD70F3402, µPD70F3403 and µPD70F3403A..................... 80
Internal ROM Area ...................................................................................................... 81
Internal RAM Area (10 KB).......................................................................................... 82
Internal RAM Area (16 KB).......................................................................................... 82
Internal Peripheral I/O Area......................................................................................... 83
Wrap-Around Using µPD70F3402 / µPD70F3403 / µPD70F3403A ............................ 84
Recommended Memory Map ...................................................................................... 85
System Wait Control Register (VSWC) Format .......................................................... 86
On-Chip Debug Mode Register (OCDM) Format ....................................................... 87
Timing Chart When On-Chip Debug Function Is Not Used ......................................... 88
Timing Chart of Transition to Normal Operation Mode................................................ 88
Timing Chart of Transition to On-Chip Debug Mode ................................................... 89
Programmable Peripheral I/O Control Register (BPC) Format ................................... 92
Port Configuration Diagram ....................................................................................... 105
Port Function Swap Control Register Format ........................................................... 111
Port Register 0 (P0) Format ..................................................................................... 112
Port Mode Register 0 (PM0) Format ......................................................................... 113
Port Mode Control Register 0 (PMC0) Format (1/2) ................................................. 113
Port Function Control Register 0 (PFC0) Format ..................................................... 114
Pull-up Resistor Option Register 0 (PU0) Format .................................................... 115
Pull-down Resistor Option Register 0 (PD0) Format ................................................ 115
External Interrupt Falling Edge Specification Register 0 (INTF0) Format ................ 116
External Interrupt Rising Edge Specification Register 0 (INTR0) Format ................. 117
Port Register 1 (P1) Format ..................................................................................... 118
Port Mode Register 1 (PM1) Format ........................................................................ 119
Port Mode Control Register 1 (PMC1) Format ......................................................... 119
Port Function Control Register 1 (PFC1) Format ..................................................... 120
Port Function Control Extended Register 1 (PFCE1) Format ................................... 120
Pull-up Resistor Option Register 1 (PU1) Format .................................................... 121
Pull-down Resistor Option Register 1 (PD1) Format ................................................ 121
External Interrupt Falling Edge Specification Register 1 (INTF1) Format ................ 122
External Interrupt Rising Edge Specification Register 1 (INTR1) Format ................. 123
Port Register 3 (P3) Format ..................................................................................... 125
Port Mode Register 3 (PM3) Format ........................................................................ 126
Port Mode Control Register 3 (PMC3) Format (1/2) ................................................. 127
User's Manual U16702EE3V2UD00 17