NEC V850E/RS1 User Manual page 276

(a) When D1 > D2 > D3; only TPnCCR0 register value is written, and TOPn0 and TOPn1
CCR0 buffer
CCR1 buffer
INTTPnCC0
INTTPnCC1
Note: The 16-bit counter is not cleared when its value matches the value of TPnCCR1.
Remarks: 1. D1, D2: Setting values of TPnCCR0 register (0000H to FFFFH)
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Chapter 7 16-Bit Timer/Event Counter P
Figure 7-18: Basic Operation Timing in Interval Timer Mode (1/2)
are not output (TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 1)
TPnCE = 1
FFFFH
D
3
16-bit
Note
counter
TPnCCR0
0000H
register
TPnCCR1
0000H
register
TOPn0
L
H
TOPn1
t
D1
D3: Setting value of TPnCCR1 register (0000H to FFFFH)
)= (Dn + 1) × (count clock cycle)
2. Interval time (t
Dn
3. n = 0 to 3
D
1
D
3
D
1
D
1
D
3
D
3
t
D1
User's Manual U16702EE3V2UD00
D
1
D
2
D
3
D
2
D
2
t
D2