NEC V850E/RS1 User Manual page 838

A.2 Instruction Set (In Alphabetical Order)
(1/4)
Mnemonic
ADD
ADDI
AND
ANDI
Bcond
BSH
BSW
CALLT
CLR1
CMOV
CMP
CTRET
DI
DISPOSE
DIV
DIVH
DIVHU
DIVU
EI
HALT
HSW
JARL
JMP
838
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Appendix A
Operand Opcode
reg1,reg2 rrrrr001110RRRRR GR[reg2]←GR[reg2] + GR[reg1]
imm5,reg2 rrrrr010010iiiii GR[reg2]←GR[reg2] + sign-extend(imm5)
rrrrr110000RRRRR
imm16,reg1,reg2
iiiiiiiiiiiiiiii
reg1,reg2 rrrrr001010RRRRR GR[reg2]←GR[reg2] AND GR[reg1]
rrrrr110110RRRRR
imm16,reg1,reg2
iiiiiiiiiiiiiiii
ddddd1011dddcccc
disp9
Note 1
rrrrr11111100000
reg2,reg3
wwwww01101000010
rrrrr11111100000
reg2,reg3
wwwww01101000000
imm6
0000001000iiiiii
10bbb111110RRRRR
bit#3, disp16[reg1]
dddddddddddddddd
rrrrr111111RRRRR
reg2,[reg1]
0000000011100100
cccc,imm5,reg2,
rrrrr111111iiiii
reg3
wwwww011000cccc0
cccc,reg1,reg2,
rrrrr111111RRRRR
reg3
wwwww011001cccc0
reg1,reg2 rrrrr001111RRRRR result←GR[reg2] – GR[reg1]
imm5,reg2 rrrrr010011iiiii result←GR[reg2] – sign-extend(imm5)
0000011111100000
0000000101000100
0000011111100000
0000000101100000
0000011001iiiiiL
imm5,list12
LLLLLLLLLLL00000
0000011001iiiiiL
imm5,list12,[reg1]
LLLLLLLLLLLRRRRR
Note 5
rrrrr111111RRRRR
reg1,reg2,reg3
wwwww01011000000
rrrrr000010RRRRR GR[reg2]←GR[reg2] ÷ GR[reg1]
reg1,reg2
rrrrr111111RRRRR
reg1,reg2,reg3
wwwww01010000000
rrrrr111111RRRRR
reg1,reg2,reg3
wwwww01010000010
rrrrr111111RRRRR
reg1,reg2,reg3
wwwww01011000010
1000011111100000
0000000101100000
0000011111100000
0000000100100000
rrrrr11111100000
reg2,reg3
wwwww01101000100
rrrrr11110dddddd
disp22,reg2
ddddddddddddddd0
Note 7
[reg1] 00000000011RRRRR PC←GR[reg1]
Instruction Set List
Operation
GR[reg2]←GR[reg1] + sign-extend(imm16)
GR[reg2]←GR[reg1] AND zero-extend(imm16)
if conditions are satisfied
then PC←PC+sign-extend(disp9)
GR[reg3]←GR[reg2] (23: 16) ll GR[reg2] (31: 24) ll
GR[reg2] (7: 0) ll GR[reg2] (15: 8)
GR[reg3]←GR[reg2] (7: 0) ll GR[reg2] (15: 8) ll
GR[reg2] (23: 16) ll GR[reg2] (31: 24)
CTPC←PC + 2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Half-word))
adr←GR[reg1] + sign-extend(disp16)
←Not(Load-memory-bit(adr,bit#3))
Z flag
Store-memory-bit(adr,bit#3,0)
adr←GR[reg1]
←Not(Load-memory-bit(adr,reg2))
Z flag
Store-memory-bit(adr,reg2,0)
if conditions are satisfied
then GR[reg3]←sign-extended(imm5)
else GR[reg3]←GR[reg2]
if conditions are satisfied
then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
PC←CTPC
PSW←CTPSW
PSW.ID←1
sp←sp + zero-extend(imm5 logically shift left by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp + 4
repeat 2 steps above until all regs in list12 are loaded
sp←sp + zero-extend(imm5 logically shift left by 2)
R[reg in list12]←Load-memory(sp,Word)
sp←sp + 4
repeat 2 steps above until all regs in list12 are loaded
PC←GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1]
GR[reg3]←GR[reg2] % GR[reg1]
Note 6
GR[reg2]←GR[reg2] ÷ GR[reg1] Note 6
GR[reg3]←GR[reg2] % GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1] Note 6
GR[reg3]←GR[reg2] % GR[reg1]
GR[reg2]←GR[reg2] ÷ GR[reg1]
GR[reg3]←GR[reg2] % GR[reg1]
PSW.ID←0
Stop
GR[reg3]←GR[reg2](15: 0) ll GR[reg2] (31: 16)
GR[reg2]←PC + 4
PC←PC + sign-extend(disp22)
User's Manual U16702EE3V2UD00
Execution
Clock
i r l CY OV S
× ×
1 1 1
× ×
1 1 1
× ×
1 1 1
1 1 1 0
1 1 1 0
2 2 2
When conditions
Note Note Note
are satisfied
2 2 2
When conditions
1 1 1
are not satisfied
×
1 1 1 0
×
1 1 1 0
4 4 4
3 3 3
Note Note Note
3 3 3
3 3 3
Note Note Note
3 3 3
1 1 1
1 1 1
× ×
1 1 1
× ×
1 1 1
3 3 3 R R
1 1 1
N+1 N+1 N+1
Note Note Note
4 4 4
N+3 N+3 N+3
Note Note Note
4 4 4
35 35 35
×
35 35 35
×
35 35 35
×
34 34 34
×
34 34 34
1 1 1
1 1 1
×
1 1 1 0
2 2 2
3 3 3
Flags
Z SAT
× ×
× ×
× ×
× ×
× ×
0
× ×
× ×
×
×
× ×
× ×
R R R
× ×
× ×
× ×
× ×
× ×