Stop Mode; Setting And Operation Status - NEC V850E/RS1 User Manual

18.6 STOP Mode

18.6.1 Setting and operation status

The STOP mode is set when the PSM1, 0 bits of the PSMR register are set to 01 and the STP bit of the
PSC register is set to 1 in the normal operation mode.
In the STOP mode, the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral
functions is stopped.
As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode
was set are retained. The on-chip peripheral functions that operate with the clock oscillated by an
external clock continue operating.
Table 18-8 shows the operation status in the STOP mode.
Because the STOP stops operation of the main clock oscillator, it reduces the current consumption to a
level lower than the IDLE2 mode. If the external clock is not used, the power consumption can be
minimized with only leakage current flowing.
Caution:
18.6.2 Releasing STOP mode
The STOP mode is released by a non-maskable interrupt request (NMI pin input, INTWDT2
occurrence), unmasked external interrupt request (INTP0 to INTP7 pin input), unmasked internal
interrupt request from the peripheral functions operable in the STOP mode, or reset signals.
After the STOP mode has been released, the normal operation mode is restored after the oscillation
stabilization time has been secured.
Caution:
(1) Releasing STOP mode by non-maskable interrupt request or unmasked maskable interrupt
request
The STOP mode is released by a non-maskable interrupt request or an unmasked maskable
interrupt request, regardless of the priority of the interrupt request. If the STOP mode is set in an
interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request with a priority lower than that of the interrupt request currently being
(b) If an interrupt request with a priority higher than that of the interrupt request currently being
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Chapter 18 Standby Function
Insert five or more NOP instructions after the instruction that stores data in the PSC
register to set the STOP mode.
An interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI1M,
and PSC.INTM bits to 1 becomes invalid and STOP mode is not released.
serviced is issued, only the STOP mode is released, and that interrupt request is not
acknowledged. The interrupt request itself is retained.
serviced is issued (including a non-maskable interrupt request), the STOP mode is released
and that interrupt request is acknowledged.
User's Manual U16702EE3V2UD00