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9.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by
option byte)
The watchdog timer stops counting during STOP instruction execution regardless of whether the high-speed
system clock or Ring-OSC clock is being used.
(1) When the CPU clock and the watchdog timer operation clock are the high-speed system clock (f
the STOP instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
and then counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 9-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: High-Speed System Clock)
Normal
operation
CPU operation
f
XP
f
R
Watchdog timer
Operating
(2) When the CPU clock is the high-speed system clock (f
Ring-OSC clock (f
) when the STOP instruction is executed
R
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
(CPU Clock: High-Speed System Clock, WDT Operation Clock: Ring-OSC Clock)
Normal
operation
CPU operation
f
XP
f
R
Watchdog timer
Operating Operation stopped
CHAPTER 9 WATCHDOG TIMER
STOP
Oscillation stabilization time
Oscillation
Oscillation stabilization time
stopped
(set by OSTS register)
Operation stopped
Figure 9-5. Operation in STOP Mode
Oscillation stabilization time
STOP
Oscillation
Oscillation stabilization time
stopped
(set by OSTS register)
Operating
Preliminary User's Manual U16846EJ1V0UD
Normal operation
) and the watchdog timer operation clock is the
XP
Normal operation
) when
XP
Operating
179
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