Sony CXD5602 User Manual page 81

3.1.4.3.31 SDIO
The following are settings that pin P1r_{00,01,02,03,04,05}, pin P1s{00,01}, pin P1t_{00,01,02}, and pin P1u_00
are assigned SDIO role.

IO_SIDO_CLK.ENZI=1

IO_SIDO_CMD.ENZI=1

IO_SIDO_DATA{0~3}.ENZI=1

IO_SIDO_CD.ENZI=1

IO_SIDO_WP.ENZI=1

IO_SIDO_CLKI.ENZI=1

IOCAPP_IOMD.SDIOA=1

IOCAPP_IOMD.SDIOB=1

IOCAPP_IOMD.SDIOC=1

IOCAPP_IOMD.SDIOD=1
Figure I/O Configuration-13 shows connecting diagram of SDIO input clock.
SDIO IP uses either clock turned inside IOCELL or clock turned outside the LSI.
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CXD5602 User Manual