Sony CXD5602 User Manual page 229

RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_DMAC3
3.8.6.3 Clock Supply Start and Stop
3.8.6.3.1 Clock Supply Start
Perform the following control to start supplying the HCLK clock of the SYSUBDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP_SUB power domain is turned ON.
2. Clock supply start
SYSIOP_SUB_CKEN.AHB_DMAC3=1'b1
3.8.6.3.2 Clock Supply Stop
1. Clock supply stop
SYSIOP_SUB_CKEN.AHB_DMAC3=1'b0
3.8.7 ADMAC
3.8.7.1 Register List
Table DMAC-89 shows the registers that control the ADMAC.
Address Register Name
0x0E020000 PrimeCell
|
0x0E020FFF
RCOSC
ck_cpu_bus
0
1
ck_rf_pll_1
1/M
2
XOSC
3
0
1
2
3
0
1
Figure DMAC-47 SYSUBDMAC Clock and Reset System
Table DMAC-81 ADMAC Control Register List
Type Description
®
Single Master DMA Controller (PL081)
－229/1010－
ck_ahb_gear
1/M
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
register
CXD5602 User Manual
SYSUBDMAC
CK
HCLK
GATE
HRESETn
initial
Value
-