Sony CXD5602 User Manual page 950

Auto(PWD_SYSIOP Power Domain ON)
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
PWD_RESET0.PWD_SYSIOP_SUB
Figure SYSIOP Clock and Reset Control-117 SYSIOP Reset Configuration Diagram
RST(0)
RST(3)
RST(8)
RST(1)
RST(2)
RST(5)
RST(7)
RST(6)
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CXD5602 User Manual
System and
I/O Processor
RST_CPU_P0_X
RST_CPU_SYS_X
SYSIOP_MAIN_BUS
HRESTn
SPI0
NSSPRST
PRESTn
UART1
nUARTRST
PRESETn
I2C2
PRESETn
AHB/APB
BusBridge
SDMAC
HRESETn
HDMAC
HRESETn
SYDMAC
HRESETn
SYSUBDMAC
HRESETn
SPI Flash Controller
HRESETn
AHB/AHB
BusBridge
Crypto
XRST_SK
SPI2
PRESTn
I2C3
PRESETn
UART0
nUARTRST
PRESETn
SEQ
XRST_HOS_SEQ
PRESETn
AHB/APB
BusBridge
FreqDisc
PRESETn
RTC0
PRESETn
RTC1
PRESETn
AHB/APB
BusBridge