Sony CXD5602 User Manual page 303

Set PWMn_THRESH to "0" and select ENABLE + UPDATE
fixed to Low Level
Set ENABLE to "0"

Setting to make PMW Output fixed status (control at PWM combining point)
Paste to H
Set PWM_SEL_INVn to "0x1" and PWM_SEL_DISn to "0x1"
Paste to L
Set PWM_SEL_INVn to "0x0" and PWM_SEL_DISn to "0x1"
3.9.11.3 Function for Synchronization with ADC (PWM to ADC)
This mode performs output of the PWM using the valid signal for the ADC output (synchronization signal)
from the ADC (LPADC/HPADC) as a reference. The following is an overview.
AD_EN
Internal
Triangular
signal
PWM output
A/D Sampling
Timing
Figure SCU (Sensor Control Unit)-84 PWM Output Mode using ADC Timing as a Reference
When setting the PWM channel n (n = 0, ..., 7), set the following registers in addition to the basic operation
settings.

PWMn_EN register
PWM_SELLn field[2:0] ... selects the ADC channel used as the reference
PWM_SELLn field[5:3]･･･fixed to "0"

PWM_PASEn register
PWM_DELAYn field
Start Phase is adjusted when the 1st AD_EN
rising after updating register setting
PWM period is
controllable
... selects the number of clocks for phase adjustment
－303/1010－
PWM start
phase is
controllable
CXD5602 User Manual