Sony CXD5602 User Manual page 942

3.14.3.4.2 Register Descriptions
Table SYSIOP Clock and Reset Control-807 shows the frequency division setting status registers of each clock.
Make sure to use the RW registers as RO registers.
Table SYSIOP Clock and Reset Control-767 Frequency Division Setting Status Registers
Address Register Name
0x041004D8 CKDIV_CPU_
DSP_BUS
Bit Field Type Bit
Name
SFC_HCL RW [31:28]
K_LOW
Reserved RO [27:26]
－942/1010－
Initial Description
Value
0
Indicated as DIV(3) in
Reset Control-116
Frequency division setting (ratio against System and
I/O Processor clock) of ck_sfc_sfclk_gear
0: divided by 1
1: divided by 2
2: divided by 3
3: divided by 4
4: divided by 5
5: divided by 6
6: divided by 7
7: divided by 8
8: divided by 9
9: divided by 10
10: divided by 16
11: divided by 32
12: divided by 64
13: divided by 128
14: divided by 256
15: divided by 512
CK_SFC_HCLK_LOW
CK_SFC_SFCLK frequency divided by 2.
E.g.
0: CK_SFC_SFCLK (divided by 1)
CK_SFC_HCLK_LOW(divided by 2)
3： CK_SFC_SFCLK(divided by 4)
CK_SFC_HCLK_LOW(divided by 8)
0 Reserved
CXD5602 User Manual
Figure SYSIOP Clock and
is always the