Sony CXD5602 User Manual page 899

Address Register Name
0x04103414 APP_CKEN
STAT_SP_C RO
LK_SEL4
STAT_APP_ RO
CLK_SEL4
APP_PLL_DI RW
V5
Reserved RW
Table APP-746 Clock Enable Registers
Bit Field Type
Name
Reserved RO
AHB RW
Reserved RO
MCLK RW
APP RW
－899/1010－
[11:10] 2'b00 Frequency division setting status for
CK_APP SYSPLL
2'b00: clock not divided
2'b01: divided by 2
2'b10: divided by 3
2'b11: divided by 4 or 5 (depending on
APP_CKSEL.APP_PLL_DIV5)
[9:8] 2'b00 Clock source switching status for
CK_APP
2'b00: RCOSC
2'b01: SYSPLL divided clock selected
by
APP_CKSEL.STAT_SP_CLK_SEL4
2'b10: XOSC
2'b11: RTC Clock
[7] 0 Clock divided by 4 or 5 for CK_APP
SYSPLL
0: clock divided by 4
1: clock divided by 5
[6:0] 0 Reserved
Bit Initial Description
Value
[31:4] 0 Reserved
[3] 0 Clock Enable of CK_APP_AHB
0: Clock stopped
1: Clock supplied
[2] 0 Reserved
[1] 0 Clock Enable of CK_APP_MCLK
0: Clock stopped
1: Clock supplied
[0] 0 Clock Enable of CK_APP
0: Clock stopped
1: Clock supplied
CXD5602 User Manual