Sony CXD5602 User Manual page 816

LPADC, SCU.AD 0x0018d
HPADC CIF e40
Power ON
0x0018d
e44
0x0018d
e50
0x0018d
e80
0x0018d
ec0
0x0018d
f80
0x0018d
fc0
0x0018d
f04
0x0018d
f00
TOPREG 0x0004
[0] LV_CLK_OSC
_SEL
[5:4] LV_CLK_XOS
C_DIV
[0] LV_BGR_EN
[0] VECTOR_SEL
[0] LV_CLK_U32_
SEL0
[0] LV_CLK_U32_
SEL1
[0] LV_ADC0_SE
LSTAGE
[7:4] LV_ADC0_DE
LAYADJUST
[0] LV_ADC1_SE
LSTAGE
[7:4] LV_ADC1_DE
LAYADJUST
[7:0] LV_RSV
[0] LV_SELSTAG
E
[29] WEN_LPADC
[13] LPADC
[28] WEN_HPADC
[12] HPADC
－816/1010－
--> The clock source selection setting during the
high speed sampling mode
0: XOSC, 1: RCOSC
--> The frequency division setting during the use
of the XOSC as clock source
0: divided by 2
1: divided by 3
2: divided by 4
3: divided by 6
1'b1 LV BGR circuit enable
--> Enable/disable of two element vector
--> Clock selection
0: High-speed clock
1: Low-speed clock
--> Clock selection
0: High-speed clock
1: Low-speed clock
1'b0 ADC0 stage selection
4'b1100 ADC0 internal clock delay amount adjustment
signal
1'b0 ADC0 stage selection
4'b1100 ADC0 internal clock delay amount adjustment
signal
8'h04
1'b0 Stage selection
1'b1 LPADC power supply control Write Enable
1'b1 LPADC power ON
1'b1 HPADC power supply control Write Enable
1'b1 HPADC power ON
CXD5602 User Manual