Sony CXD5602 User Manual page 235

0x04123100 DMACSrcAddr_n
(n=0-3,step=0x20)
0x04123104 DMACDestAddr_n
(n=0-3,step=0x20)
0x04123108 DMACLLI_n
(n=0-3,step=0x20)
0x0412310C DMACExtControl_n
(n=0-3,step=0x20)
Indicates
information
channel's transfer size,
burst size, transfer data
width, etc. during the
DMA data transfer. This
register must
before the corresponding
DMA channel is enabled.
When Scatter/Gather
transfer
performed, it will be
automatically updated to
the value
corresponding linked list.
DMACSR
EQMASK
SRCADD
R
DESTADD
R
-
I
the control
of each
DI
be set
SI
is being
of the
－235/1010－
RW [15:0] 0
RW [31:0] 0
RW [31:0] 0
RW [31:0] 0
RW [31] 1'b0
RW [30] 1'b0
RW [29] 1'b0
CXD5602 User Manual
Masks the input of the DMA data transfer
request input terminal DMASREQ[15:0].
When masked, only DMABREQ[15:0]
becomes valid.
0: DMASREQ input is masked
1: DMASREQ input is valid
Note that the setting of this register
changes the handshake method between
the DMAC and Peripherals and should be
used with care. When single data transfer
requests are disabled, only burst requests
can be accepted.
Same as PL080
Same as PL080
Same as PL080
When DMACConfiguration.TS=1
(TransferSize expanded mapping)
The enable bit for terminal count
interrupt, which controls whether the
current LLI is expected to trigger the
terminal count interrupt.
When DMACConfiguration.TS=1
(TransferSize expanded mapping)
Controls whether or not to increment the
destination address.
0: No increment
1: Increments each time a transfer occurs
When DMACConfiguration.TS=1
(TransferSize expanded mapping)
Controls whether or not to increment the
source address.
0: No increment
1: Increments each time a transfer occurs