Sony CXD5602 User Manual page 895

and PWD_APP_AUD. The following describes each functional block of the Application Domain and the
corresponding power domains.

PWD_APP

All components of Application Domain

Including 1.5 MByte SRAM in Application memory and Application Multi-layer Bus

PWD_APP_DSP

Application & DSP processors

ADMAC

PWD_APP_SUB

Connectivity, Storage I/F and Camera, Display Interface in Application Domain

PWD_APP_AUD

Audio Codec
3.13.3 Clock Reset Control
3.13.3.1 Overview of APP Maximum Frequency
From Table APP-766 to Table APP-775 describe the APP maximum operating frequencies of the APP MAIN Bus
and the APP SUB Bus to which main functional blocks of the Application Domain are connected. Each has a
different maximum operating frequency depending on the supported XOSC frequency and the SYSPLL
oscillating frequency. In addition, element circuits such as AudioCodec, USB, eMMC, that are connected to the
APP SUB Bus, have the same maximum frequencies as the APP MAIN Bus.
For the maximum operating frequencies of external communication interfaces, refer to separate sections.
Clock source
frequency
APP M AIN Bus/APP SUB Bus
Clock source
frequency
APP M AIN Bus/APP SUB Bus
Table APP-742 XOSC (26 MHz), High Performance Mode
M Hz
M Hz
Table APP-743 XOSC (26 MHz), Low Power Mode
M Hz
M Hz
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SYSPLL XOSC
195.000 156.000 26.000
97.500 156.000 26.000
SYSPLL XOSC
195.000 156.000 26.000
39.000 39.000 26.000
CXD5602 User Manual
RCOSC RTC
8.192 0.032768
8.192 0.032768
RCOSC RTC
8.192 0.032768
8.192 0.032768