Sony CXD5602 User Manual page 886

3.11.2.3 Clock supply Start and Stop
3.11.2.3.1 Clock Supply Start
Perform the following control to start supplying the UARTCLK clock and PCLK clock to the UART1.
1. Clock supply start to the AHB/APB Bus Bridge
SYSIOP_SUB_CKEN.COM_BRG=1'b1
SYSIOP_SUB_CKEN.AHB_BRG_COMIF=1'b1
2. Reset release
SWRESET_BUS.XRST_UART1=1'b1
3. Clock supply start
SYSIOP_SUB_CKEN.COM_UART_PCLK=1'b1
SYSIOP_SUB_CKEN.UART1=1'b1
3.11.2.3.2 Clock Supply Stop
Perform the following control to stop supplying the UARTCLK clock and PCLK clock to the UART1.
1. Clock supply stop
SYSIOP_SUB_CKEN.COM_UART_PCLK=1'b0
SYSIOP_SUB_CKEN.UART1=1'b0
3.11.3 UART2
3.11.3.1 Register List
Table UART-765 shows a register list of the UART2.
Address Register Name
0x0E103000 PrimeCell
|
0x0E103048
0x0E10304C Reserved
|
0x0E1033FC
Table UART-741 UART2 Register List
Type Description
®
UART (PL011) register
RO Reserved
－886/1010－
CXD5602 User Manual
Initial
Value
-
0x0