Sony CXD5602 User Manual page 887

3.11.3.2 Clock and Reset
Figure UART-101 shows the clock and reset system diagram of the UART2.
RTC_CLK_IN(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
APP_CKSEL.APP_PLL_DIV5
APP_CKSEL.STAT_SP_CLK_SEL4
APP_CKSEL.STAT_APP_CLK_SEL4
APP_CKEN.APP
3.11.3.3 Clock Supply Start and Stop
3.11.3.3.1 Clock Supply Start
Perform the following control to start supplying the UARTCLK clock and PCLK clock to the UART2.
1. Reset release
PWD_RESET0.PWD_APP=1'b1
RESET.xrs_img=1'b1
2. Supply the CK_APP (For details, refer to the APP Section (3.13))
3. Clock supply for the UART2 register and division ratio setting
GEAR_AHB.gear_m_ahb=(arbitrary: denominator setting of the division ratio)
GEAR_AHB.gear_n_ahb=(arbitrary: numerator setting of the division ratio)
CK_GATE_AHB.ck_gate_img=1'b1
4. UART2 control clock supply and division ratio setting
GEAR_IMG_UART.gear_m_uart=(arbitrary: denominator setting of the division ratio)
GEAR_IMG_UART.gear_n_uart=1'b1
RCOSC
0
1
CK_APP
CK
2
XOSC
GATE
3
0
1
2
3
0
1
GEAR_IMG_WSPI.gear_m_img_wspi
GEAR_IMG_WSPI.gear_n_img_wspi
Figure UART-101 UART2 Clock and Reset System
GEAR_AHB.gear_m_ahb
GEAR_AHB.gear_n_ahb
CK_GATE_AHB.ck_gate_img
GEAR_IMG_SPI.gear_m_spi
GEAR_IMG_SPI.gear_n_spi
GEAR_IMG_UART.gear_m_uart
GEAR_IMG_UART.gear_n_uart
RESET.xrs_img
PWD_RESET0.PWD_APP
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CXD5602 User Manual
N/M
CK
GATE
CK
1/M
SSPCLK
GATE
PCLK
nSSPRST
PRESETn
CK
1/M
SSPCLK
GATE
PCLK
nSSPRST
PRESETn
CK
1/M
UARTCLK
GATE
PCLK
nUARTRST
PRESETn
SPI4
SPI5
UART2