Sony CXD5602 User Manual page 240

0x04123114 DMACDefLLI_n
(n=0-3,step=0x20)
The register for setting
the DefLLI. Does not
perform
update.
When
DMACConfiguration.D
LLI=1 (DefLLI function
exists), this
exists.
When
DMACConfiguration.D
LLI=0 (DefLLI function
does not exist), all bits
become Reserved.
When writing, set to "0",
when reading, mask it.
0x04123500 DMACITCR
0x04123504 DMACITOP1
0x04123508 DMACITOP2
0x0412350C DMACITOP3
0x04123800 DMACAUX0
0x04123804 DMACAUX1
0x04123808 DMACAUX2
0x0412380C DMACAUX3
DEFLLI RW
automatic
DEFLE RW
register
DEFLM RW
- RW
- RW
- RW
- RW
AUX_0 RW
AUX_1 RW
AUX_2 RW
AUX_3 RW
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[31:2] 0 The address that points to the Default
Linked List Item. When transfer starts
with the DefLLI function enabled, the LLI
of the address that DefLLI points to is
read before starting data transfer, and
following
DestAddr, LLI, and Control, the transfer
starts.
[1] 0 Selects enable/disable of the DefLLI
function.
0: Disabled
1: Enabled
[0] 0 Sets the AHB bus master channel that
becomes active when the DefLLI is
loaded.
0: Selects AHB master 1
1: Selects AHB master 2
[31:0] 0 Same as PL080
[31:0] 0 Same as PL080
[31:0] 0 Same as PL080
[31:0] 0 Same as PL080
[31:0] 0 Any data can be set
[31:0] 0 Any data can be set
[31:0] 0 Any data can be set
[31:0] 0 Any data can be set
CXD5602 User Manual
the update of SrcAddr,