Sony CXD5602 User Manual page 214

3.7.2.1 Register List
Table I2C-80 shows a register list of the I2C0 and I2C1.
Address Register Name
0x0418D400 I2C0 register (For details, refer to the API)
|
0x0418D7FC
0x0418D800 I2C1 register (For details, refer to the API)
|
0x0418DBFC
3.7.2.2 Clock and Reset
Figure I2C-39 shows the clock and reset system of the I2C0 and I2C1.
Before accessing the I2C0 or I2C1 registers, make sure to set SCU_CKEN.SCU=1'b1.
RCOSC
RTC_CLK_IN
(32.768kHz)
CKSEL_SCU.SEL_SCU_32K
XOSC
CKSEL_SCU.SEL_SCU_XTAL
CKSEL_SCU.SEL_SCU
The I2C0 and I2C1 are integrated within the SCU, and clock control is possible by the System and I/O Processor
or sequencer of the SCU. For clock gating control of the I2CCLK, there is control using the register and control
using the sequencer, and the clock is supplied when either is in the supply setting.
The clock source can be selected from: the RCOSC; the clock generated by dividing the XOSC; the RCOSC
divided by 250; or the RTC.
Table I2C-72 I2C0 and I2C1 Register List
Type Description
1/250
0
1
Reserved
0
1/2
1
1/3
2
1/4 3
Figure I2C-39 I2C0/I2C1 Clock and Reset System
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0
1
ck_scu_pre
2
3
SCU_CKEN.SCU_I2C0
Control by sequencer
SCU_CKEN.SCU_I2C1
Control by sequencer
PWD_RESET0.PWD_SCU
SWRESET_SCU.XRST_SCU_I2C0
SWRESET_SCU.XRST_SCU_I2C1
CXD5602 User Manual
initial
Value
-
-
I2C0
CK
I2CCLK
GATE
PCLK
PRESETn
I2C1
CK
I2CCLK
GATE
PCLK
PRESETn