Sony CXD5602 User Manual page 900

Address Register Name
0x0E011000 GEAR_AHB
0x0E011004 GEAR_IMG_UART
0x0E011008 GEAR_IMG_SPI
0x0E01100C GEAR_PER_SDIO
Table APP-747 Clock Reset Generator Registers
Bit Field Type
Name
Reserved RO
gear_n_ahb RW
Reserved RO
gear_m_ahb RW
Reserved RO
gear_n_uart RW
Reserved RO
gear_m_uart RW
Reserved RO
gear_n_spi RW
Reserved RO
gear_m_spi RW
Reserved RO
－900/1010－
Bit Initial Description
Value
[31:23] 0 Reserved
[22:16] 7'h1 Division ratio setting of AHB bus clock
(numerator)
"0" must not be written (because "0"
will be overwritten to "1")
[15:7] 0 Reserved
[6:0] 7'h2 Division ratio setting of AHB bus clock
(denominator) "0" or values which are
applicable to the formula "gear_n_ahb >
gear_m_ahb" must not be written.
(If that is done, gear_n_ahb will be
overwritten to 7'h7f, and
gear_m_ahb, to 7'h7f. (Operationally,
it means 1/1.)
[31:17] 0 Reserved
[16] 0 UART2 Clock Enable
0: Clock stopped
1: Clock supplied
[15:7] 0 Reserved
[6:0] 7'h4 Division ratio setting of UART2 clock
(denominator)
"0" must not be written.
[31:17] 0 Reserved
[16] 0 SPI4 Clock Enable
0: Clock stopped
1: Clock supplied
[15:7] 0 Reserved
[6:0] 7'h4 Division ratio setting of SPI4 clock
(denominator)
"0" must not be written.
[31:17] 0 Reserved
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