Sony CXD5602 User Manual page 898

3.13.3.3 Register Descriptions
The following describes setting registers for clock and reset.
Clock division ratio setting and clock switching registers are controlled by the API. The clock setting can be
confirmed with the registers described in Table APP-776 and Table APP-777. Make sure to use them as RO
registers.
Address Register Name
0x0410341C APP_DIV
Address Register
Name
0x04103418 APP_CKSEL
Table APP-744Clock Division Ratio Setting Registers
Bit Field
Name
Reserved
AU_MCLK
Table APP-745 Clock Switching Registers
Bit Field
Name
Reserved
AU_MCLK
Reserved
－898/1010－
Type Bit Initial
Value
RO [31:3] 0
RW [2:0] 0
Type Bit Initial
Value
RO [31:18] 0
RW [17:16] 2'b00
RO [15:12] 0
CXD5602 User Manual
Description
Reserved
AUDIO XOSC division ratio setting
0: clock not divided
1: clock divided by 2
2: clock divided by 3
3: clock divided by 4
4: clock divided by 5
5: clock divided by 6
6: clock divided by 7
7: clock divided by 8
Description
Reserved
Clock source switching for AUDIO
2'b00: External MCLK
2'b01: XOSC divided clock selected by
APP_DIV.AU_MCLK
2'b10: RCOSC
2'b11: Prohibited setting
Reserved