Sony CXD5602 User Manual page 143

GNSS PWD_GNSS_ITP
Domain
PWD_GNSS
SRAM (GNSS BB#0)
SRAM (GNSS BB#1)
SRAM (GNSS BB#2)
SRAM (GNSS BB#3)
SRAM (GNSS BB#4)
SRAM (GNSS BB#5)
RF (LNA)
RF (MIX)
RF (IF)
RF (ADC)
RF (LO)
RF (PLL)
2. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
3. Interrupt mask cancel
PMU_INT_MASK.MSK[1:0]=2'b00
4. Power supply control execution
PMU_PW_CTL.POWER_CTRL_ON=1
5. Interrupt confirmation
Confirm PMU_INT_STAT.STAT[1:0]=2'b01
In the case of PMU_INT_STAT.STAT[1]=1, refer to Section 3.4.3.7.
6. Interrupt clear
PMU_INT_CLR.CLR[1:0]=2'b11
7. Clock and reset control
Perform proper clock and reset control according to each power domain, SRAM, and Analog circuit.
Power Supply Control Restrictions
When power domains such as the SRAM are turned ON, make sure to turn ON all SRAMs in those power
domains. The following describes an example of the power supply control setting.

In the case of turning ON the PWD_APP (SRAM (Application Processor Tile #0-11) ON)

PWD_CTL=0x01000100 (PWD_APP=ON)

APPDSP_RAMMODE_SEL0=0x3F000FFF (SRAM (Application Processor Tile #0-5) =ON)

APPDSP_RAMMODE_SEL1=0x3F000FFF (SRAM (Application Processor Tile #6-11) =ON)

In the case of turning ON the PWD_GNSS (SRAM (GNSS BB#0-5) ON)

PWD_CTL=0x20002000 (PWD_GNSS=ON)
PWD_CTL
PWD_CTL
GNSS_RAMMODE_SEL
GNSS_RAMMODE_SEL
GNSS_RAMMODE_SEL
GNSS_RAMMODE_SEL
GNSS_RAMMODE_SEL
GNSS_RAMMODE_SEL
ANA_PW_CTL
ANA_PW_CTL
ANA_PW_CTL
ANA_PW_CTL
ANA_PW_CTL
ANA_PW_CTL
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CXD5602 User Manual
0x10000000 0x10001000
0x20000000 0x20002000
0x01000000 0x01000003
0x02000000 0x0200000C
0x04000000 0x04000030
0x08000000 0x080000C0
0x10000000 0x10000300
0x20000000 0x20000C00
0x00100000 0x00100010
0x00200000 0x00200020
0x00400000 0x00400040
0x00800000 0x00800080
0x01000000 0x01000100
0x02000000 0x02000200
－
－
0x01000001
0x02000004
0x04000010
0x08000040
0x10000100
0x20000400
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