Sony CXD5602 User Manual page 892


AES Encryption/Decryption

ECB, CBC, CTR, OFB, and CFB and CMAC chaining algorithms, 128, 192 or 256 bit key

Key generation

Up to 128 bit
Embedded Application Memory
The key features include:

1.5 MByte SRAM

operating frequency

High Performance mode: Up to 156.0 MHz

Low Power mode: Up to 39.0 MHz
Image and Display Processing Domain
The key features Domain include:

8 bit parallel Camera Interface input

8 bit ITU-R BT.601/656 Mode

compressed data like JPEG supported

supports Y/C, JPEG and JPEG+Y/C Interleave formats

Programmable polarity of video sync signal

Capture frame control supported

Input image size

JPEG Only

Y/C Only

JPEG+Y/C

Parallel Input rate: Up to 54 MHz

SPI Interface for external display

PrimeCell ® Synchronous Serial Port (PL022)

Display resolution

High Performance mode: Up to 320 240 15 fps 24 bit RGB

Low Power Mode: Up to 176 x 144, 15 fps 24 bit RGB

Communication at speeds

High Performance mode:

Master Half duplex mode: up to 39 Mbit/s (transmit only)

Master Full duplex mode: up to 9.75 Mbit/s

Low Power mode:

Master Half duplex mode: up to 9.75 Mbit/s (transmit only)

Master Full duplex mode: up to 6.5 Mbit/s

SPI Interface for Wi-Fi
: up to 5 M pixels
: up to 480 x 360
: 2 M + WQVGA (JPEG High Quality mode)
5 M + WQVGA (JPEG Normal Quality mode)
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CXD5602 User Manual