Sony CXD5602 User Manual page 159

MCLK
24.576kHz
XOSC
XTAL
26MHz
≒8.192MHz
RCOSC
RTC Clock
32.768kHz
Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme
Clock for Logic
XOSC macro
Clock for SYSPLL xo_pllclk
CK
ANA(4) GATE
XOSC
Clock for Logic
CK
ANA(2) GATE
XTAL
Clock for HPADC CK_XOSC
CK
(Refer to SCU)
ANA(3) GATE
16.368MHz
19.2MHz
XO_LV_LOCLK CK_RF_REF
CK
(Refer to GNSS)
26MHz ANA(5) GATE
32.736MHz
52MHz
RCOSC macro
ro_senclk
Clock for HPADC
CK
(Refer to SCU)
ANA(1) GATE
RCOSC
Clock for Logic
CK
ANA(0) GATE
RTC Clock
(32.768kHz)
Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme
Divider
Divider
Divider
Divider
163.68MHz
196.416MHz
SYSPLL
Max199.2MHz
RF
1/250
Divider
SYSPLL macro
SYSPLL
CK
ANA(7) GATE
1/2
Clock for RF CK_RF_ADC 1/3
CK
ANA(6) GATE
1/4
1/5
(Refer to SCU)
－159/1010－
Application Domain
Divider
Divider
Divider
Divider
100MHz(High performance mode)
/ 32MHz(Low Power mode)
Divider
Divider
GNSS Domain
66.4MHz(RFPLL)/65.472MHz(SYSPLL)
Divider
16.6MHz(RFPLL)/16.368MHz(SYSPLL)
Divider
Always On
32KHz / 8.192MHz
32KHz
(Refer to SYSIOP)
0
ck_rf_pll_1
1
ck_cpu_bus
1/M
2
3
SEL(4)
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
CKDIV_CPU_DSP_BUS.CK_APB
0
1
2
3
0
1
SEL(2)
SEL(1)
0
ck_sel_ro_rtc
RCRTC
1
1/250
0
1
Reserved ck_rtc_pre
2
SEL(3)
3
Reserved
SEL(5)
CXD5602 User Manual
163MHz(High performance mode)
/ 40MHz(Low Power mode) Application
AHB
Divider
Peripheral
49.104MHz
2D Graphics
49.104MHz
System and IOP Domain
System and I/O
AHB
SYSIOP Bus
APB
Divider Peripheral
Sensor Domain
100MHz(High performance mode)
/ 32MHz(Low Power mode)
Divider GNSS DSP
ck_cpu_bus_gear_1
CK
CG(3) GATE
ck_ahb_gear
1/M
CK
CG(2) GATE
1/M ck_apb_gear
0
1
2 CK
CG(1) GATE
3
Reserved
SEL(6)
CK
CG(0) GATE
Processor
APP Bus
CIS I/F
USB
SDIO
eMMC
AUDIO
Processor
Debug
BB
ITP
PMU
RTC
System and IOP
Fabric
BackUp SRAM
CK_PWD_RAM
Crypto(Clefia)
PCLK
HCLK
Always On
I2C4
I2CCLK
PCLK
Register
CK_RTC_APB
PMU
CK_PMU