Sony CXD5602 User Manual page 226

3.8.4.1 Register List
Table DMAC-86 shows the registers that control the HDMAC.
Address Register Name
0x04121000 PrimeCell
|
0x04121FFC
3.8.4.2 Clock and Reset
Figure DMAC-45 shows the clock and reset system diagram of the HDMAC.
Reset of the HDMAC is automatically released when the PWD_SYSIOP power domain is turned ON.
RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_CKEN.AHB_DMAC1
3.8.4.3 Clock Supply Start and Stop
3.8.4.3.1 Clock Supply Start
Perform the following control to start supplying the HCLK clock of the HDMAC.
1. Reset release
Automatically released when the PWD_SYSIOP power domain is turned ON.
2. Clock supply start
SYSIOP_CKEN.AHB_DMAC1=1'b1
Table DMAC-78 HDMAC Control Register List
Type Description
®
Single Master DMA Controller (PL081)
RCOSC
ck_cpu_bus
0
1
ck_rf_pll_1
1/M
2
XOSC
3
0
1
2
3
0
1
Figure DMAC-45 HDMAC Clock and Reset System
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register
ck_ahb_gear
1/M
Auto(PWD_SYSIOP Power Domain ON)
CXD5602 User Manual
initial
Value
-
HDMAC
CK
HCLK
GATE
HRESETn