Sony CXD5602 User Manual page 306

PWM output
Data Enable
HPADC output
(Channel 0)
HPADC output
(Channel 1)
FIFO Write
Timing
Figure SCU (Sensor Control Unit)-85 ADC Data Capture Mode using the PWM Output Timing as a Reference
When setting the PWM channel n (n = 0, ..., 7), set the following registers in addition to the basic operation
settings.

PWM_PASExx register
PWM_CNTENn field[15:8] ... sets the capture start position (3 to 255)

PWM_PASExx register
PWM_CNTENn field[7:4]... sets the number of captures (1 to 15)

PWMn_EN register
PWM_SELLn field [2:0] ... selects the ADC channel used as the reference
PWM_SELLn field [5:3]･･･fixed to "0"
Enable control of this synchronization function is controlled by the PWMn_EN field of the PWMn_EN register
and synchronization operation starts by using the Writing to the PWMn_UPDATE register as a trigger.
The following is an example of the basic settings.
[1]Setting of the PWM to which data capture timing of the ADC is synchronized
HPADC0_D1 DECI_RATIO2 /HPADC1_D1 DECI_RATIO2/LPADC_D0
DECI_RATIO2/LPADC_D1 DECI_RATIO2/LPADC_D2 DECI_RATIO2/LPADC_D3 DECI_RATIO2
[2] Setting the number of data captured by the ADC
PWM_PASExx PWM_CNTENn [15:8] and [7:4] must not be "0"
[3]The Synchronization ADC is set
PWMn_EN PWM_SELLn Synchronization ADC channel setting
[4]The PWM starts
PWMxx_EN/PWMcxx_UPDATE is executed
The selection of which channel's signal of the PWM to assign to each ADC channel is set by the registers on
Capture timing is
controllable
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CXD5602 User Manual
The number of
capture data is
controllable