Sony CXD5602 User Manual page 962

For details, refer to Section3.9.4.6 , Clock Control from Internal Sequencers described in Chapter of the CPU.
3.21.6 Reset Control
The following describes main reset control of the LPADC and the HPADC.
For Peripheral Name information, refer to Table Memory Mapping-2 of the section 2.6.2, Memory Map of each
block.
Target Peripheral Name
LPADC PMU, CRG, GPIO, I/O Config
HPADC PMU, CRG, GPIO, I/O Config
3.21.7 Interrupt
The ADCIF is equipped in the SCU. For the details of the interrupt, refer to the chapter 3.3, Interrupt.
3.21.8 FIFO writing Process
The following describes the data flow.
LPADC0
LPADC1
LPADC2
LPADC3
HPADC0
HPADC1
After being started, the ADC refers the status of the NOT_EMPTY interrupt from the ADCIF, then begins to
move. When the status is NOT_EMPTY, the ADC reads out the data and transfer them to the Write FIFO in the
SCU.
Table ADC-776 Main Reset Control
Address bit
0x0704 [4]
0x0704 [2]
ADCIF
Figure ADC-121 Data Flow of the ADC
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Name Set
Value
XRST_SCU_LPADC 1'b1
XRST_SCU_HPADC 1'b1
MATH_PROC
Sequencer
Processing
CXD5602 User Manual
Remarks
0: Reset
1: Reset release
FIFO