Sony CXD5602 User Manual page 885

3.11.2 UART1
3.11.2.1 Register List
Table UART-764 shows a register list of the UART1.
Address Register Name
0x041AC000 PrimeCell
|
0x041AC048
0x041AC04C Reserved
|
0x041ACFFC
3.11.2.2 Clock and Reset
Figure UART-100 shows the clock and reset system diagram of the UART1.
To access the UART1 register, supply the clock to the AHB/APB Bus Bridge.
RTC_CLK_IN
(32.768kHz)
SYSPLL
1/2
1/3
1/4
1/5
CKSEL_ROOT.CPU_PLL_DIV5
CKSEL_ROOT.RFPLL1_STAT_CLK_SEL4
CKSEL_ROOT.STAT_CLK_SEL4
SYSIOP_SUB_CKEN.COM_BRG
SYSIOP_SUB_CKEN.UART1
SYSIOP_SUB_CKEN.COM_UART_PCLK
CKDIV_CPU_DSP_BUS.CK_M0
CKDIV_CPU_DSP_BUS.CK_AHB
SYSIOP_SUB_CKEN.AHB_BRG_COMIF
Table UART-740 UART1 Register List
Type Description
®
UART (PL011) register
RO Reserved
RCOSC
0
ck_rf_pll_1
1 ck_cpu_bus
2
XOSC
3 1/M
0
1
2
3
0
1
CKDIV_COM.CK_COM
1/M
Figure UART-100 UART1 Clock and Reset System
－885/1010－
ck_co m_gear
CK_COM_BRG
CK
GATE
ck_ahb_gear
1/M
Auto(PWD_SYSIOP_SUB Power Domain ON)
PWD_RESET0.PWD_SYSIOP_SUB
SWRESET_BUS.XRST_UART1
CXD5602 User Manual
Initial
Value
-
0x0
UART1
CK
UARTCLK
GATE
PCLK
nUARTRST
PRESETn
CK
GATE
AHB/APB
BusBridge
CK
GATE