Sony CXD5602 User Manual page 154

3.4.5 Power Supply Control Example
3.4.5.1 Actual Example of Power Supply Control
By ORing the power supply control setting (PWD_CTL, *_RAMMODE_SEL, ANA_PW_CTL) of each power
supply, you can control multiple power supplies together by a single power supply control request
(PMU_PW_CTL.POWER_CTRL_ON). The PMU recognizes the upper layer and lower layer of the power
supplies and automatically controls the order of the power supply switch control. When controlling the power
supply from OFF to ON, the control is started from the power supplies in the upper layer. Conversely, when
controlling the power supply from ON to OFF, the control is started from the lower layer. The following describes
an example of power supply control.
Power supplies to control

PWD_APP (OFF=>ON)

PWD_APP_AUD (OFF=>ON)

PWD_SCU (ON=>OFF)

SRAM (Application Processor Tile #4) (OFF=>ON)
Power supply control flow
1. Power supply control setting
PWD_CTL=0x41014100
OR the following power supply control settings

PWD_CTL=0x01000100 (PWD_APP=ON)

PWD_CTL=0x40004000 (PWD_APP_AUD=ON)

PWD_CTL=0x00010000 (PWD_SCU=ON)
APPDSP_RAMMODE_SEL0=0x3F000FFF
Note:
Due to the power supply control restrictions, turn ON all SRAMs of the PWD_APP layer.
OR the following power supply control settings

APPDSP_RAMMODE_SEL0=0x01000003 (SRAM (Application Processor Tile #0) =ON)

APPDSP_RAMMODE_SEL0=0x0200000C (SRAM (Application Processor Tile #1) =ON)

APPDSP_RAMMODE_SEL0=0x04000030 (SRAM (Application Processor Tile #2) =ON)

APPDSP_RAMMODE_SEL0=0x080000C0 (SRAM (Application Processor Tile #3) =ON)

APPDSP_RAMMODE_SEL0=0x10000300 (SRAM (Application Processor Tile #4) =ON)

APPDSP_RAMMODE_SEL0=0x20000C00 (SRAM (Application Processor Tile #5) =ON)
APPDSP_RAMMODE_SEL1=0x3F000FFF
OR the following power supply control settings

APPDSP_RAMMODE_SEL1=0x01000003 (SRAM (Application Processor Tile #6) =ON)
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CXD5602 User Manual