Table of Contents
Advertisement
21
PRELIMINARY
PRELIMINARY
Read and write timing (continued from the preceding page)
Symbol
t
Data Output Delay Time after Write
d(BLWL-D)
t
(Byte write mode)
d(BHWL-D)
t
Valid Data Output Time after Write
v(BLWH-D)
t
(Byte write mode)
v(BHWH-D)
t
Data Output Disable Time after Write
pxz(BLWH-DZ)
t
(Byte write mode)
pxz(BHWH-DZ)
Address Delay Time before Write
t
d(A-WRL)
(Byte enable mode)
Chip Select Delay Time before Write
t
d(CS-WRL)
(Byte enable mode)
Valid Address Time after Write
t
v(WRH-A)
(Byte enable mode)
Valid Chip Select Time after Write
t
v(WRH-CS)
(Byte enable mode)
t
Byte enable delay time before write
d(BLE-WRL)
t
(Byte enable mode)
d(BHE-WRL)
t
Byte enable delay time after write
v(WRH-BLE)
t
(Byte enable mode)
v(WRH-BHE)
Data Output Delay Time after Write
t
d(WRL-D)
(Byte enable mode)
Valid Data Output Time after Write
t
v(WRH-D)
(Byte enable mode)
Data output disable time after write
t
pxz(WRH-DZ)
(Byte enable mode)
t
Read high-level pulse width
w(RDH)
(5) Bus arbitration
Symbol
t
HACK Delay Time after BCLK
d(BCLKL-HACKL)
t
v(BCLKL-HACKL)
Valid HACK Time after BCLK
Parameter
Parameter
21-17
ELECTRICAL CHARACTERISTICS
21.5 AC Characteristics
Condition
Rated Value
MIN
tc(BCLK)
-13
2
tc(BCLK)
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-15
2
tc(BCLK)
-13
2
tc(BCLK)
tc(BCLK)
-3
2
Rated Value
Condition
MIN
-11
See
Unit
Figure
21.5.6
21.5.7
MAX
21.5.8
52
15
ns
ns
53
+5
ns
54
2
ns
69
ns
70
ns
71
ns
72
ns
73
ns
74
15
ns
75
ns
76
+5
ns
77
2
55
ns
See
Unit
Figure
MAX
21.5.9
ns
29
37
ns
38
Ver.0.10
Advertisement
Table of Contents
