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10
TML1 Measure 3 Register (TML1MR3H)
TML1 Measure 3 Register (TML1MR3L)
TML1 Measure 2 Register (TML1MR2H)
TML1 Measure 2 Register (TML1MR2L)
TML1 Measure 1 Register (TML1MR1H)
TML1 Measure 1 Register (TML1MR1L)
TML1 Measure 0 Register (TML1MR0H)
TML1 Measure 0 Register (TML1MR0L)
D0
1
2
D0
1
2
D
Bit Name
0-15
TML1MR3H-0H
TML1MR3L-0L
Note 1: These registers are a read-only register.
Note 2: These registers must always be accessed in words (32 bits) beginning with a word boundary.
The TML1 Measure Registers are used to latch counter contents upon event input. The TML1
Measure Registers are configured with 32 bits, the TML1MR3H-0H accommodating the 16 high-
order bits, and the TML1MR3L-0L accommodating the 16 low-order bits. The TML1 Measure
Registers are a read-only register. These registers must always be accessed in words (32 bits)
beginning with a word boundary.
3
4
5
6
TML1MR3H-TML1MR0H (16 high-order bits)
3
4
5
6
TML1MR3L-TML1MR0L (16 low-order bits)
10-157
MULTIJUNCTION TIMERS
10.6 TML (Input-related 32-bit Timer)
7
8
9
10
11
7
8
9
10
11
Function
32-bit counter value (16 high-order bits)
32-bit counter value (16 low-order bits)
<Address: H'0080 0FF0>
<Address: H'0080 0FF2>
<Address: H'0080 0FF4>
<Address: H'0080 0FF6>
<Address: H'0080 0FF8>
<Address: H'0080 0FFA>
<Address: H'0080 0FFC>
<Address: H'0080 0FFE>
12
13
14
D15
12
13
14
D15
<When reset: Indeterminate>
R
Ver.0.10
W
–
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