Mitsubishi Electric M32R Series User Manual page 234

9
9.2 DMAC Related Registers
The diagram below shows a memory map of DMAC related registers.
Address
H'0080 0400
H'0080 0408
H'0080 0410
H'0080 0412
H'0080 0414
H'0080 0416
H'0080 0418
H'0080 041A
H'0080 041C
H'0080 041E
H'0080 0420
H'0080 0422
H'0080 0424
H'0080 0426
H'0080 0428
H'0080 042A
H'0080 042C
H'0080 042E
H'0080 0430
H'0080 0432
H'0080 0434
H'0080 0436
H'0080 0438
H'0080 043A
H'0080 043C
H'0080 043E
Blank addresses are reserved.
Note: The registers enclosed in thick frames can only be accessed in halfwords.
Figure 9.2.1 DMAC Related Register Map (1/2)
+0 Address
D0
DMA0-4 Interrupt Request Status
Register (DM04ITST)
DMA5-9 Interrupt Request Status
Register (DM59ITST)
DMA0 Channel Control
Register (DM0CNT)
DMA0 Source Address Register (DM0SA)
DMA0 Destination Address Register (DM0DA)
DMA5 Channel Control
Register (DM5CNT)
DMA5 Source Address Register (DM5SA)
DMA5 Destination Address Register (DM5DA)
DMA1 Channel Control
Register (DM1CNT)
DMA1 Source Address Register (DM1SA)
DMA1 Destination Address Register (DM1DA)
DMA6 Channel Control
Register (DM6CNT)
DMA6 Source Address Register (DM6SA)
DMA6 Destination Address Register (DM6DA)
DMA2 Channel Control
Register (DM2CNT)
DMA2 Source Address Register (DM2SA)
DMA2 Destination Address Register (DM2DA)
DMA7 Channel Control
Register (DM7CNT)
DMA7 Source Address Register (DM7SA)
DMA7 Destination Address Register (DM7DA)
9-4
9.2 DMAC Related Registers
+1 Address
D7 D8
DMA0-4 Interrupt Mask
Register (DM04ITMK)
DMA5-9 Interrupt Mask
Register (DM59ITMK)
DMA0 Transfer Count
Register (DM0TCT)
DMA5 Transfer Count
Register (DM5TCT)
DMA1 Transfer Count
Register (DM1TCT)
DMA6 Transfer Count
Register (DM6TCT)
DMA2 Transfer Count
Register (DM2TCT)
DMA7 Transfer Count
Register (DM7TCT)
DMAC
D15
Ver.0.10