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12
12.2.2 SIO Interrupt Control Registers
SIO23 Interrupt Status Register (SI23STAT)
D0
D
Bit Name
0 - 3
No functions assigned
4
IRQT2 (SIO2 transmit-finished
interrupt request status bit) 1 : Interrupt requested
5
IRQR2 (SIO2 receive interrupt
request status bit)
6
IRQT3 (SIO3 transmit-finished
interrupt request status bit) 1 : Interrupt requested
7
IRQR3 (SIO3 receive interrupt
request status bit)
W =
: Only writing a 0 is effective; when you write a 1, the previous value is retained.
Transmit/receive interrupt requests from SIO2 and SIO3 are described below.
[Setting the interrupt request status bit]
This bit can only be set in hardware, and cannot be set in software.
[Clearing the interrupt request status bit]
This bit is cleared by writing a 0 in software.
Note : If the status bit is set in hardware at the same time it is cleared in software, the
former has priority and the status bit is set.
When writing to the SIO Interrupt Status Register, make sure the bits you want to clear are set to 0
and all other bits are set to 1. The bits which are thus set to 1 are unaffected by writing in software
and retain the value they had before you write.
1
2
3
Function
0 : Interrupt not requested
0 : Interrupt not requested
1 : Interrupt requested
0 : Interrupt not requested
0 : Interrupt not requested
1 : Interrupt requested
12-9
12.2 Serial I/O Related Registers
<Address: H'0080 0100>
4
5
6
IRQT2
IRQR2
IRQT3
SERIAL I/O
D7
IRQR3
<When reset : H'00>
R
W
0
—
Ver.0.10
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