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12
SIO03 Cause of Receive Interrupt Select Register (SI03SEL) <Address: H'0080 0102>
D0
D
Bit Name
0 - 3
No functions assigned
4
ISR0 (SIO0 receive interrupt
cause select bit)
5
ISR1 (SIO1 receive interrupt
cause select bit)
6
ISR2 (SIO2 receive interrupt
cause select bit)
7
ISR3 (SIO3 receive interrupt
cause select bit)
This register selects the cause of an interrupt generated at completion of receive operation.
[When set to 0]
Receive-finished interrupt (receive buffer full) is selected. Receive-finished interrupts
occur for receive errors (except an overrun error), as well as for completion of receive
operation.
[When set to 1]
Receive error interrupt is selected. The following lists the types of errors detected for
reception errors.
• CSIO mode : Overrun error
• UART mode : Overrun error, parity error, and framing error
1
2
3
Function
0 : Receive-finished interrupt
1 : Receive error interrupt
0 : Receive-finished interrupt
1 : Receive error interrupt
0 : Receive-finished interrupt
1 : Receive error interrupt
0 : Receive-finished interrupt
1 : Receive error interrupt
12-13
12.2 Serial I/O Related Registers
4
5
6
ISR0
ISR1
ISR2
SERIAL I/O
D7
ISR3
<When reset : H'00>
R
W
0
—
Ver.0.10
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