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20
5V
0V
Figure 20.3.5 CPU Halt State
0V
0V
3.3V-2.0V
Figure 20.3.6 SRAM Data Backup State
POWER-UP/POWER-SHUTDOWN SEQUENCE
5V power supply
3.3V power supply
5V power supply
3.3V power supply
20.3 Power-Shutdown Sequence
M32R/E
VCCE
I/O control circuit
AVCC
A-D converter circuit
VCCI
CPU
Peripheral circuits
VDD
RAM
FVCC
Flash
OSC-VCC
Oscillator and PLL circuits
M32R/E
VCCE
I/O control circuit
AVCC
A-D converter circuit
VCCI
CPU
Peripheral circuits
VDD
RAM
FVCC
Flash
OSC-VCC
Oscillator and PLL circuits
20-8
Ver.0.10
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