Transfer Counts; Address Space - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

9.3.6 Transfer Units

Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16

bits) to be transferred in one DMA transfer.

9.3.7 Transfer Counts

Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be

performed up to 256 times. The value of the DMA Transfer Count Register is decremented by one

each time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register

operates in free-run mode, with the value set in it ignored.

The address space in which data can be transferred by DMA is the internal peripheral I/O or 64

Kbytes of RAM space (H'0080 0000 through H'0080 FFFF) for either source or destination. To set

the source and destination addresses in each channel, use the DMA Source Address Register and

DMA Destination Address Register.

9.3.9 Transfer Operation

(1) Dual-address transfer

Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read

access and one for destination write access. (The transfer data is temporarily taken into the

DMA's internal temporary register.)

(2) Bus protocol and bus timing

Because the bus interface is shared with the CPU, the same applies to both bus protocol and bus

timing as in peripheral module access from the CPU.

(3) Transfer rate

The maximum transfer rate is calculated using the equation below:

Maximum transfer rate [bytes/second] = 2 bytes ×

9.3 Functional Description of the DMAC

1 / f (BCLK) × 3 cycles