Mitsubishi Electric M32R Series User Manual page 501

11
Table 11.1.1 outlines the A-D converters. Figures 11.1.1 and 11.1.2 show block diagrams of A-D0
and A-D1 converters, respectively.
Table 11.1.1 Outline of A-D Converters
Item
Analog input
A-D conversion method
Resolution
Nonlinearity error (Note1) (Conditions: Normal rate mode
Ta = 25°C,AVCC0,1=VREF0,1=5.12V)
Conversion mode
Operation mode
Scan mode
Conversion start trigger
Conversion rate
f(BCLK):
Internal peripheral clock
operating frequency
Interrupt request generation function
DMA transfer request generation
function (Note 4)
Note 1: The nonlinearity error is a deviation from ideal conversion characteristics after the offset and full-scale
errors are adjusted to 0.
Note 2: Refer to Chapter 10, "Multijunction Timers."
Note 3: When BCLK = 20 MHz, this is 1/f(BCLK) = 50 ns.
Note 4: The DMA transfer request generation function is available for only the A-D0 converter. The A-D1
converter does not have this function.
Content
16 channels x 2
Successive approximation method
10 bits (Conversion results can be read out in either 8 bits or 10 bits)
Double rate mode
A-D conversion mode, comparator mode
Single mode, scan mode
Single-shot scan mode, continuous scan mode
Software start
Hardware start
During single mode
(shortest time)
During comparator mode Normal rate
(shortest time)
Generated at completion of A-D conversion, comparate operation,
single-shot scan operation, or one cycle of continuous scan operation
Generated at completion of A-D conversion, comparate operation,
single-shot scan operation, or one cycle of continuous scan operation
11-3
A-D CONVERTERS
11.1 Outline of A-D Converters
±2LSB
±2LSB
Started by setting A-D converter start bit to 1
A-D0 converter started by MJT output event
bus 3, A-D1 converter started by TID1
overflow or underflow (Note 2)
__________
Started by external ADTRG pin input
299 × 1/f(BCLK) (Note 3)
Normal rate
173 × 1/f(BCLK)
Double rate
47 × 1/f(BCLK)
29 × 1/f(BCLK)
Double rate
Ver.0.10