2
2.3 Control Registers
There are five control registers-Processor Status Word Register (PSW), Condition Bit Register
(CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC).
Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers.
Notes 1: CRn (n = 0-3, 6) denotes control register numbers.
2: Dedicated "MVTC" and "MVFC" instructions are used to set and read the control registers.
Figure 2.3.1 Control Registers
Control Registers
CRn
0
CR0
PSW
CR1
CBR
CR2
SPI
CR3
SPU
CR6
BPC
2-3
31
Processor status Word Register
Condition Bit Register
Interrupt Stack Pointer
User Stack Pointer
Backup PC
CPU
2.3 Control Registers
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