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10
Clock bus
TIN1
TIN1S
Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted.
Figure 10.3.6 Outline Diagram of TOP6, TOP7 Clock/Enable Inputs
Input event bus
3 2 1 0
3 2 1 0
S
S
: Selector
S
10-74
MULTIJUNCTION TIMERS
10.3 TOP (Output-related 16-bit Timer)
clk
TOP 6
en
clk
TOP 7
en
S
udf
udf
Ver.0.10
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