Outline Of Interrupt Controller (Icu) - Mitsubishi Electric M32R Series User Manual

5

5.1 Outline of Interrupt Controller (ICU)

The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a
system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to
the M32R CPU as external interrupts (EI).
There are a total of 31 interrupt sources for the maskable interrupts from internal peripheral I/Os,
which are managed by assigning them one of eight priority levels including an interrupt-disabled
state. When multiple interrupt requests of the same priority level occur simultaneously, their
priorities are resolved by predetermined hardware priority. The source of an interrupt request
generated in internal peripheral I/Os is identified by reading the relevant interrupt status register
provided for internal peripheral I/Os.
On the other hand, the system break interrupt (SBI) is recognized when a low-going transition
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occurs on the SBI signal input pin. This interrupt is used for emergency purposes such as when
power outage is detected or a fault condition is notified by an external watchdog timer, so that it is
always accepted irrespective of the PSW register IE bit status. When the ICU has finished servicing
an SBI, terminate or reset the system without returning to the program that was being executed
when the interrupt occurred.
Specifications of the interrupt controller are outlined in the table below.
Table 5.1.1 Outline of Interrupt Controller (ICU)
Item
Interrupt source
Level management
Specification
Maskable interrupt from internal peripheral I/O : 31 sources
System break interrupt
Eight levels including an interrupt-disabled state
(However, interrupts of the same level have their priorities resolved by fixed
hardware priority.)
5-2
INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller (ICU)
: 1 source (entered from SBI pin)
Ver.0.10