Mitsubishi Electric M32R Series User Manual page 585

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

Transmit clock

Transmit enable bit

Transmit buffer

Transmit status bit

SIO transmit interrupt

Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit

Note 2 : When transmit interrupt is enabled (DMA transfer can also be requested at the same timing)

Note 3 : Transmit interrupt request is generated when transmission is enabled.

Note 4 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated

when the data is transferred from the transmit buffer to the transmit shift register and the transmit

buffer is thereby emptied.

Figure 12.3.4 Example of CSIO Transmission (Successive Transmission, with Transmit

Buffer Empty and Transmit Finished Interrupts Used)

Internal clock selected

(First data)

: Processing by software

12.3 Transmit Operation in CSIO Mode

External clock selected

Upon transmit buffer empty

interrupt, next data is written

: Interrupt generation