Mitsubishi Electric M32R Series User Manual page 259

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Table 9.3.6 Causes of DMA Requests in DMA5 and Generation Timings
REQSL5 Cause of DMA Request
0 0 Software start
or one DMA7 transfer completed
0 1 All DMA0 transfers completed
1 0 Serial I/O2 (reception completed)
1 1 MJT (TIN20 input signal)
Table 9.3.7 Causes of DMA Requests in DMA6 and Generation Timings
REQSL6 Cause of DMA Request
0 0 Software start
0 1 Serial I/O1 (transmit buffer empty)
1 0 MJT (TIN1 input signal)
1 1 One DMA5 transfer completed
Table 9.3.8 Causes of DMA Requests in DMA7 and Generation Timings
REQSL7 Cause of DMA Request
0 0 Software start
0 1 Serial I/O2 (transmit buffer empty)
1 0 MJT (TIN2 input signal)
1 1 One DMA6 transfer completed
9.3 Functional Description of the DMAC
DMA Request Generation Timing
When any data is written to DMA5 Software Request
Generation Register or one DMA7 transfer is completed
(cascade mode)
When all DMA0 transfers are completed (cascade mode)
When serial I/O2 reception is completed
When MJT's TIN20 input signal is generated
DMA Request Generation Timing
When any data is written to DMA6 Software Request
Generation Register
When serial I/O1 transmit buffer is emptied
When MJT's TIN1 input signal is generated
When one DMA5 transfer is completed (cascade mode)
DMA Request Generation Timing
When any data is written to DMA7 Software Request
Generation Register
When serial I/O2 transmit buffer is emptied
When MJT's TIN2 input signal is generated
When one DMA6 transfer is completed (cascade mode)
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DMAC
Ver.0.10