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9
The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel,
set DMA transfer request flag, and the bits to select the cause of DMA request, enable DMA
transfer, and set the transfer size and the source/destination address directions.
(1) MDSELn (DMAn transfer mode select) bit (D0)
This bit when in single transfer mode selects normal mode or ring buffer mode. Normal mode is
selected by setting this bit to 0 or ring buffer mode is selected by setting it to 1.
In ring buffer mode, transfer begins from the transfer start address and after performing transfers
32 times, control is recycled back to the transfer start address, from which transfer operation is
repeated. In this case, the Transfer Count Register counts in free-run mode during which time
transfer operation is continued until the transfer enable bit is reset to 0 (to disable transfer). No
interrupt is generated at completion of DMA transfer.
(2) TREQFn (DMAn transfer request flag) bit (D1)
This flag is set to 1 when a DMA transfer request occurs. Reading this flag helps to know DMA
transfer requests in each channel.
The generated DMA request is cleared by writing a 0 to this bit. If you write a 1, the value you
wrote is ignored and the bit retains its previous value. If a new DMA transfer request is generated
for a channel whose DMA transfer request flag has already been set to 1, the next DMA transfer
request is not accepted until the transfer under way in that channel is completed.
(3) REQSLn (cause of DMAn request select) bits (D2, D3)
These bits select the cause of DMA request in each DMA channel.
(4) TENLn (DMAn transfer enable) bit (D4)
Transfer is enabled by setting this bit to 1, so that the channel is ready for DMA transfer.
Conversely, transfer is disabled by setting this bit to 0. However, if a transfer request has already
been accepted, transfer in that channel is not disabled until after the requested transfer is
completed.
(5) TSZSLn (DMAn transfer size select) bit (D5)
This bit selects the number of bits to be transferred in one DMA transfer operation (unit of one
transfer). The unit of one transfer is 16 bits when TSZSL = 0 or 8 bits when TSZSL = 1.
(6) SADSLn (DMAn source address direction select) bit (D6)
This bit selects the direction in which the source address changes as transfer proceeds. This
mode can be selected from two choices: address fixed or address incremental.
(7) DADSLn (DAMn destination address direction select) bit (D7)
This bit selects the direction in which the destination address changes as transfer proceeds. This
mode can be selected from two choices: address fixed or address incremental.
9-16
9.2 DMAC Related Registers
Ver.0.10
DMAC
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