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4
4.9.3 External Interrupt (EI)
An external interrupt is generated upon an interrupt request which is output by the 32170's internal
interrupt controller. The interrupt controller manages interrupt requests by assigning each one of
seven priority levels. For details, refer to Chapter 5, "Interrupt Controller." For details about the
interrupt sources, refer to each section in which the relevant internal peripheral I/O is described.
[Occurrence Conditions]
External interrupts are managed based on interrupt requests from each internal peripheral I/O by
the 32170's internal interrupt controller. These interrupt requests are notified to the M32R CPU
by the interrupt controller. The M32R/E checks these interrupt requests at a break in instructions
residing on word boundaries, and when an interrupt request is detected and the PSW register IE
flag = 1, accepts it as an external interrupt.
In no case will an external interrupt be activated immediately after executing a 16-bit instruction
that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt may be
accepted immediately after branching.)
Address 1000
16-bit instruction
Interrupt may
be accepted
Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted
Order in which instructions are executed
Address 1002
Address 1004
16-bit instruction
Interrupt
Interrupt may
cannot be
be accepted
accepted
4-18
4.9 Interrupt Processing
32-bit instruction
Interrupt may
be accepted
EIT
Address 1008
Ver.0.10
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