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19
19.5 Boundary Scan Description Language
The Boundary Scan Description Language (abbreviated BSDL) is stipulated in supplements to
"Standard Test Access Port and Boundary-Scan Architecture" of IEEE 1149.1-1990 and IEEE
1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description
Language (VHDL). BSDL helps to precisely describe the functions of standard-compliant
components to be tested. For package connection test, this language is used by Automated Test
Pattern Generation tools, and for synthesized test logic and verification, it is used by Electronic
Design Automation tools. BSDL provides powerful extended functions usable in internal test
generation and necessary to write hardware debug and diagnostics software.
The primary section of BSDL contains statements of logical port description, physical pin map,
instruction set, and boundary register description.
• Logical port description
The logical port description assigns meaningful symbol names to each pin on the chip. This
determines the logic type of input, output, input/output, buffer, or link of each pin that defines the
logical direction of signal flow.
• Physical pin map
The physical pin map correlates the chip's logical ports to the physical pins on each package.
Use of separate names for each map makes it possible to define multiple physical pin maps in
one BSDL description.
• Instruction set statement
The instruction set statement writes bit patterns to be shifted in into the chip's instruction register.
This bit pattern is necessary to place the chip into each test mode defined in standards. It is also
possible to write instructions exclusive to the chip.
• Boundary register description
The boundary register description is a list of boundary register cells or shift stages. Each cell is
assigned a separate number. The cell with number 0 is located closest to the test data output
(JTDO) pin, and the cell with the largest number is located closest to the test data input (JTDI)
pin. Cells also contain related other information which includes cell type, logical port
corresponding to cell, logical function of cell, safety value, control cell number, disable value, and
result value.
The BSDL for the 32170 shown in the pages to follow have been prepared for use in test
engineering for the purpose of PCB design and those stipulated in IEEE 1149.1 standards.
19.5 Boundary Scan Description Language
19-14
JTAG
Ver.0.10
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