Mitsubishi Electric M32R Series User Manual page 569

12
The SIO Mode Register consists of bits to set the serial I/O operation mode, data format, and the
functions used during communication.
The SIO Transmit/Receive Mode Register must always be set before serial I/O starts operating. If
you want to change settings of this register after the serial I/O started transmitting or receiving data,
be sure to confirm that transmit and receive operations have been completed and disable transmit/
receive operations (by clearing the SIO Transmit Control Register transmit enable bit and SIO
Receive Control Register receive enable bit to 0) before you change.
(1) SMOD (serial I/O mode select) bits
These bits select the operation mode of serial I/O.
(2) CKS (internal/external clock select) bit
This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode
is selected, in which case the serial I/O is clocked by an internal clock.
(3) STB (stop bit length select) bit
This bit is effective when UART mode is selected. Use this bit to select the stop bit length that
indicates the end of data to transmit. Setting this bit to 0 selects one stop bit, and setting this bit
to 1 selects two stop bits. During clock-synchronous mode, the content of this bit has no effect.
(4) PSEL (parity odd/even select) bit
This bit is effective during UART mode. When parity is enabled (D14 = 1), use this bit to select the
parity attribute (whether odd or even). Setting this bit to 0 selects an odd parity, and setting this bit
to 1 selects an even parity. When parity is disabled (D14 = 0) and during clock-synchronous
mode, the content of this bit has no effect.
(5) PEN (parity enable) bit
This bit is effective during UART mode. When this bit is set to 1, a parity bit is added immediately
after the data bits of transmit data, and for receive data, the parity in it is checked. The parity bit
added to the transmit data is automatically determined to be a 1 or a 0 in such a way that the
attribute (odd/even) of the sum of the number of 1's in data bits and the content of the parity bit
agrees with one selected by the parity odd/even select bit (D13). Figure 12.2.4 shows an
example of data format when parity is enabled.
(6) SEN (sleep select) bit
This bit is effective during UART mode. If the sleep function is enabled by setting this bit to 1, data
is latched into the UART Receive Buffer Register only when the most significant bit (MSB) of the
received data is 1.
(D8 to D10)
(D11)
(D12)
(D13)
(D14)
(D15)
12-19
12.2 Serial I/O Related Registers
SERIAL I/O
Ver.0.10