Mitsubishi Electric M32R Series User Manual page 555

12
SIO0
SIO0 Transmit Buffer Register
TXD0 SIO0 Transmit Shift Register
SIO0 Receive Shift Register
RXD0
SIO0 Receive Buffer Register
BCLK
SIO1
TXD1 SIO1 Transmit Shift Register
RXD1 SIO1 Receive Shift Register
SIO2
TXD2
SIO2 Transmit Shift Register
RXD2 SIO2 Receive Shift Register
SIO3
TXD3
SIO3 Transmit Shift Register
RXD3 SIO3 Receive Shift Register
SIO4
SIO4 Transmit Shift Register
TXD4
RXD4 SIO4 Receive Shift Register
SIO5
TXD5 SIO5 Transmit Shift Register
SIO5 Receive Shift Register
RXD5
Note 1 : When BCLK is selected, the BRG set value is subject to limitations.
Note 2 : SIO2 and SIO3 do not have the SCLKI/SCLKO function.
Figure 12.1.1 Block Diagram of SIO0-SIO5
Transmit/receive
control circuit
UART
mode
BCLK,
1/16
BCLK/8,
1
BCLK/32,
(Set value + 1)
BCLK/256
Baud rate
Clock divider
generator (BRG)
Transmit/receive
control circuit
Transmit/receive
control circuit
Transmit/receive
control circuit
Transmit/receive
control circuit
Transmit/receive
control circuit
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
CSIO
mode
When external clock selected
When internal clock selected
1/2
CSIO mode
When internal clock selected
When UART mode selected
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
Transmit interrupt
Receive interrupt
Transmit interrupt
Receive interrupt
12-5
SERIAL I/O
12.1 Outline of Serial I/O
To interrupt
controller
To DMAC3
To DMAC4
SCLKI0/ SCLKO0
To interrupt
controller
To DMAC6
To DMAC3
SCLKI1/ SCLKO1
To DMAC7
To DMAC5
To interrupt
controller
To DMAC9
To DMAC8
SCLKI4 / SCLKO4
To interrupt
controller
SCLKI5 / SCLKO5
Ver.0.10