Ram Backup State - Mitsubishi Electric M32R Series User Manual

17

17.3.2 RAM Backup State

Figure 17.3.3 shows the RAM backup state of the M32R/E. Figure 17.3.4 shows a RAM backup
sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A
low on these input pins generates a RAM backup signal (A and
backup mode, make the following settings.
(1) Create check data to verify after returning from RAM backup to normal mode whether the
RAM data has been retained normally (
(2) To materialize low-power operation, set all programmable input/output pins except port X for
input mode (or for output mode, with pins outputting a low) (
(3) Set port X for input mode (B and
voltage, IB, to go low, so that no current flows from the power supply to the VCC pin via the
transistor (C in Figure 17.3.3). Consequently, the power to the VCC pin is shut off (D in Figure
17.3.3).
Due to settings in (1) to (3), the voltage applied to the VDD pin becomes 3.3 V ± 10% and voltages
applied to all other pins drop to 0 V, thus placing the M32R/E in RAM backup mode (
DC IN
Input
External circuit
RAM backup
signal (Note 1)
Example of RAM
backup processing
Generate RAM backup signal
Set transistor's base
connecting pin (port X) for
input mode (Note 5)
RAM backup mode
Figure 17.3.3 RAM Backup State for Low-Power Operation
17.3 Example of RAM Backup for Saving Power Consumption
C
IB
"L"
"L"
"L"
A
"L"
SBI
ADnINi
(Note 4)
Create check data
for backup RAM
in Figure 17.3.3).
in Figure 17.3.3). This causes the transistor's base
Output
Regulator
(3.3V system)
D
Output
Regulator
(5V system)
Output
Regulator
(3.3V system)
B
0V 0V
"L"
Port X
VCCI OSC-VCC VCCE
(Note 2)
(Note 3)
Note 1: This signal outputs a low for RAM backup.
Note 2: This pin outputs a high when the power is on, and
is set for input mode when in RAM backup mode.
Note 3: These pins are used to detect a RAM backup
signal.
Note 4: Determined by the input voltage level on SBI pin
or ADnINi pin.
Note 5: Base voltage IB = 0 causes the current fed to the
VCC pin to stop. Explained in A to D above.
17-7
RAM BACKUP MODE
___
in Figure 17.3.3). To enable RAM
in Figure 17.3.3).
in Figure 17.2.3).
Power supply for RAM
0V 0V 0V
VREFn AVCCn VDD
M32R/E
3.3V
___
Ver.0.10