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19
19.1 Outline of JTAG
The 32170 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test
Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can
be used as an input/output path for boundary-scan test (boundary-scan path). For details about
IEEE 1149.1 JTAG test access ports, refer to the IEEE Std. 1149.1a-1993 documentation.
The functions of JTAG interface related pins mounted on the 32170 are shown below.
Table 19.1.1 JTAG Pin Functions
Type
Symbol Pin Name
TAP
JTCK
(Note)
JTDI
JTDO
JTMS
JTRST
Note : TAP = Test Access Port, a JTAG interface stipulated in IEEE 1149.1.
I/O
Test clock
Input
Test data input
input
Test data output
output
Test mode select
Input
Test reset
Input
Function
Clock input to the test circuit.
Synchronous serial data input pin used to enter test
instruction code and test data. This input is sampled on
rising edges of JTCK.
Synchronous serial data output pin used to output test
instruction code and test data. This signal changes state on
falling edges of JTCK, and is output only in Shift-IR or Shift-
DR state.
Test mode select input to control the test circuit's state
transitions. This input is sampled on rising edges of JTCK.
Active-low test reset input to initialize the test circuit
asynchronously. To ensure that the test circuit is reset
without fail, JTMS signal input must be held high while this
signal changes state from low to high.
19-2
JTAG
19.1 Outline of JTAG
Ver.0.10
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